Nicolas Delfosse

Quantum low-density parity-check (qLDPC) codes are a class of quantum error-correction (QEC) codes with low-weight parity-checks that each require only a few two-qubit gates to implement. In recent years, qLDPC codes have gained popularity, as concrete code constructions have been found that outperform the surface code, and correspondingly performant practical decoders have been built. An outstanding challenge, however, remains that their Tanner graphs are not 2D-local thereby necessitating entangling gates to operate on distant qubits on a 2D device. Trapped-ion and neutral-atom qubits possess the ability to move qubits around when necessary – i.e. “flying qubits” – obviating the need for long-range gates. Here we report on an explicit layout that leverages flying qubits, that is very low-overhead for many families of cyclic codes (including the most promising qLDPC instances found to-date). Crucially, our layout eschews more complicated qubit permutations, and instead favours the cyclic shift a simple re-ordering of qubits along a loop that can be realized in depth 1 even on current generation devices. This contrasts significantly with layouts on fixed qubits that depend on a large number of long-range (and more error-prone) hardware couplers for long-distance gates. We also report on two competitive new sets of cyclic qLDPC codes that we constructed. The first is a set of Bivariate-Bicycle (BB) codes with lower weight parity-checks and higher minimum distance while maintaining the same length and encoding rate as comparable BB codes in. Second, we also constructed new Hypergraph Product (HGP) codes, that significantly outperform previously state-of-the-art HGP instances that were optimized by machine-learning methods. Both sets of new codes are efficiently implementable with our cyclic layout with syndrome circuits of fixed depth, made up of alternating layers of parallel gates and only a very small number of cyclic shifts. Combining competitive new qLDPC codes alongside a simple layout implementable on existing hardware, our work suggest a concrete and practical path towards a fault-tolerant quantum computer.

Quantum computation promises significant computational advantages over classical computation for some problems. However, quantum hardware suffers from much higher error rates than in classical hardware. As a result, extensive quantum error correction is required to execute a useful quantum algorithm. The decoder is a key component of the error correction scheme whose role is to identify errors faster than they accumulate in the quantum computer and that must be implemented with minimum hardware resources in order to scale to the regime of practical applications. In this work, we consider surface code error correction, which is the most popular family of error correcting codes for quantum computing, and we design a decoder micro-architecture for the Union-Find decoding algorithm. We propose a three-stage fully pipelined hardware implementation of the decoder that significantly speeds up the decoder. Then, we optimize the amount of decoding hardware required to perform error correction simultaneously over all the logical qubits of the quantum computer. By sharing resources between logical qubits, we obtain a 67% reduction of the number of hardware units and the memory capacity is reduced by 70%. Moreover, we reduce the bandwidth required for the decoding process by a factor at least 30x using low-overhead compression algorithms. Finally, we provide numerical evidence that our optimized micro-architecture can be executed fast enough to correct errors in a quantum computer.

Neutral atom quantum computers and to a lesser extent trapped ions may suffer from atom loss. In this work, we investigate the impact of atom loss in long chains of trapped ions. Even though this is a relatively rare event, ion loss in long chains must be addressed because it destabilizes the entire chain resulting in the loss of all the qubits of the chain. We propose a solution to the chain loss problem based on (1) a quantum error correction code distributed over multiple long chains, (2) beacon qubits within each long chain to detect the loss of a chain, and (3) a decoder adapted to correct a combination of circuit faults and erasures after beacon qubits convert chain losses into erasures. We verify the chain loss correction capability of our scheme through circuit level simulations with a distributed $[[72,12,6]]$ BB code with beacon qubits.

We propose a decoder for quantum low density parity check (LDPC) codes based on a beam search heuristic guided by belief propagation (BP). Our beam search decoder applies to all quantum LDPC codes and achieves different speed-accuracy tradeoffs by tuning its parameters such as the beam width. We perform numerical simulations under circuit level noise for the $[[144, 12, 12]]$ bivariate bicycle (BB) code at noise rate $p=10^{-3}$ to estimate the logical error rate and the 99.9 percentile runtime and we compare with the BP-OSD decoder which has been the default quantum LDPC decoder for the past six years. A variant of our beam search decoder with a beam width of 64 achieves a $17\times$ reduction in logical error rate. With a beam width of 8, we reach the same logical error rate as BP-OSD with a $26.2\times$ reduction in the 99.9 percentile runtime. We identify the beam search decoder with beam width of 32 as a promising candidate for trapped ion architectures because it achieves a $5.6\times$ reduction in logical error rate with a 99.9 percentile runtime per syndrome extraction round below 1ms at $p=5 \times 10^{-4}$. Remarkably, this is achieved in software on a single core, without any parallelization or specialized hardware (FPGA, ASIC), suggesting one might only need three 32-core CPUs to decode a trapped ion quantum computer with 1000 logical qubits.

The main bottleneck for distributed quantum computing is the rate at which entanglement is produced between quantum processing units (QPUs). In this work, we prove that multiple QPUs connected through slow interconnects can outperform a monolithic architecture made with a single QPU. We present a distributed version of Clifford noise reduction (CliNR), a partial error correction scheme, and show that it outperforms a monolithic version of CliNR. Distributed CliNR has lower depth and lower logical error rates than monolithic CliNR even when the interconnects are slow. In simulations we show that the advantage persists with interconnects that are five times slower than two qubit gates. We also prove a sufficient condition for distributed CliNR to outperform monolithic CliNR. In addition, we present two methods for improving CliNR, allowing lower logical error rates and efficient performance for arbitrary length Clifford circuits. Finally we present results from an experimental implementation of a variant of CliNR on an ion trap quantum computer. This work is based on three papers that are available on arXiv (see extended abstract).