Taofiq K Paraiso

Random numbers play a crucial role in information technology, particularly as digital communication capacity continues to expand. Consequently, the need for secure and high-rate random number generation has become increasingly urgent. While integrated photonics technology holds promise for mass-producing optoelectronic quantum random number generators (QRNGs), there remains a challenge in developing fast, robust, and scalable solutions suitable for industrial deployment. Addressing this challenge, we present a fast QRNG solution in this study, leveraging a photonic integrated circuit (PIC) directly embedded onto a versatile electronic platform. Designed to withstand real-world applications, our PIC is packaged to align with industrial electronic assembly lines. To rigorously assess scalability and stability, these generators underwent week-long periods of continuous GHz operation. Furthermore, a QRNG was integrated into a quantum key distribution system, where despite operating in an uncontrolled environment, minimal variations in physical randomness were observed over 38 days, as measured from 2.9 million histograms. Finally, we implemented a security model for the QRNGs, enabling rate adjustment to match the actual randomness content and demonstrating secure generation at 2 Gbit/s.

Hybrid integration has the potential to overcome various limitations of integrated photonic material platforms. Here, we present the results of applying edge-couple hybrid integration to produce high performance quantum key distribution chips. We show low quantum bit error rate operation (< 1%) and positive secure key rates over 250 km of fibre spool.

As the volume of data and connections exchanged across telecom/datacom networks continues to increase, there is a growing need for technologies that deploy quantum key distribution (QKD) on a large scale in a practical and sustainable manner. To realize high-speed, real-time communication of large-volume data using one-time pad cryptography with QKD modules, it will be important to multiplex QKD modules in the future. Furthermore, it is necessary to consider the physical size of the device for the practical application of multiplexed QKD modules. In this study, we focused on miniaturizing the key distillation process required at the back end of the QKD chip. To reduce the size of the device, it is necessary to estimate as accurately as possible the minimum computing power required to run the key distillation process for the target secret key rate (SKR). However, the performance of the key distillation process requires computing power and involves the exchange of messages via classical channels. Therefore, we evaluate the performance by a network simulator before performing evaluations on the actual equipment. In this paper, we focus on the behavior of classical communication paths in the multiplexed QKD system, which is a problem in studying the key distillation process, and we evaluate it with the simulator. Specifically, we clarify the relationship between the required performance of the key distillation process (i.e., throughput) and the target SKR, which is necessary to realize a part of the key distillation process in hardware.